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LA-ispMACH 4000V/Z Automotive Family
3.3V/1.8V In-System Programmable SuperFAST TM High Density PLDs
July 2008 Data Sheet DS1017
Features
High Performance
* fMAX = 168MHz maximum operating frequency * tPD = 7.5ns propagation delay * Up to four global clock pins with programmable clock polarity control * Up to 80 PTs per output
Ease of Design
* Enhanced macrocells with individual clock, reset, preset and clock enable controls * Up to four global OE controls * Individual local OE control per I/O pin * Excellent First-Time-FitTM and refit * Fast path, SpeedLockingTM Path, and wide-PT path * Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders
* 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces * Hot-socketing * Open-drain capability * Input pull-up, pull-down or bus-keeper * Programmable output slew rate * 3.3V PCI compatible * IEEE 1149.1 boundary scan testable * 3.3V/2.5V/1.8V In-System Programmable (ISPTM) using IEEE 1532 compliant interface * I/O pins with fast setup path * Lead-free (RoHS) package
Introduction
The high performance LA-ispMACH 4000V/Z automotive family from Lattice offers a SuperFAST CPLD solution that is tested and qualified to the AEC-Q100 standard. The family is a blend of Lattice's two most popular architectures: the ispLSI(R) 2000 and ispMACH 4A. Retaining the best of both families, the LA-ispMACH 4000V/Z architecture focuses on significant innovations to combine the highest performance with low power in a flexible CPLD family. The LA-ispMACH 4000V/Z automotive family combines high speed and low power with the flexibility needed for ease of design. With its robust Global Routing Pool and Output Routing Pool, this family delivers excellent FirstTime-Fit, timing predictability, routing, pin-out retention and density migration.
Zero Power (LA-ispMACH 4000Z)
* Typical static current 10A (4032Z) * 1.8V core low dynamic power * LA-ispMACH 4000Z operational down to 1.6V
AEC-Q100 Tested and Qualified
* Automotive: -40 to 125C ambient (TA)
Easy System Integration
* Superior solution for power sensitive consumer applications * Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O * Operation with 3.3V (4000V) or 1.8V (4000Z) supplies
Table 1. LA-ispMACH 4000V Automotive Family Selection Guide
LA-ispMACH 4032V Macrocells I/O + Dedicated Inputs tPD (ns) tS (ns) tCO (ns) fMAX (MHz) Supply Voltage (V) Pins/Package 32 30+2/32+4 7.5 4.5 4.5 168 3.3V 44-pin Lead-Free TQFP 48-pin Lead-Free TQFP LA-ispMACH 4064V 64 30+2/32+4/64+10 7.5 4.5 4.5 168 3.3V 44-pin Lead-Free TQFP 48-pin Lead-Free TQFP 100-pin Lead-Free TQFP LA-ispMACH 4128V 128 64+10/92+4/96+4 7.5 4.5 4.5 168 3.3V
100-pin Lead-Free TQFP 128-pin Lead-Free TQFP 144-pin Lead-Free TQFP
(c) 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
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DS1017_02.3
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Table 2. LA-ispMACH 4000Z Automotive Family Selection Guide
LA-ispMACH 4032Z Macrocells I/O + Dedicated Inputs tPD (ns) tS (ns) tCO (ns) fMAX (MHz) Supply Voltage (V) Pins/Package 32 32+4 7.5 4.5 4.5 168 1.8V 48-pin Lead-Free TQFP LA-ispMACH 4064Z 64 32+4/64+10 7.5 4.5 4.5 168 1.8V 48-pin Lead-Free TQFP 100-pin Lead-Free TQFP LA-ispMACH 4128Z 128 64+10 7.5 4.5 4.5 168 1.8V 100-pin Lead-Free TQFP
The LA-ispMACH 4000V/Z automotive family offers densities ranging from 32 to 128 macrocells. There are multiple density-I/O combinations in Thin Quad Flat Pack (TQFP) packages ranging from 44 to 144 pins. Tables 1 and 2 show the macrocell, package and I/O options, along with other key parameters. The LA-ispMACH 4000V/Z automotive family has enhanced system integration capabilities. It supports 3.3V (4000V and 1.8V (4000Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The LAispMACH 4000V/Z also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. The LA-ispMACH 4000V/Z automotive family is in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary scan testing capability also allows product testing on automated test equipment. The 1532 interface signals TCK, TMS, TDI and TDO are referenced to VCC (logic core).
Overview
The LA-ispMACH 4000V/Z automotive devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which contain multiple I/O cells. This architecture is shown in Figure 1. Figure 1. Functional Block Diagram
CLK0/I CLK1/I CLK2/I CLK3/I VCCO0 GND VCCO1 GND I/O Block ORP I/O Bank 1 16 36 Generic 16 Logic Block I/O Block ORP GOE0 GOE1 VCC GND TCK TMS TDI TDO
I/O Block ORP I/O Bank 0 16
Global Routing Pool
Generic Logic Block
16 36
16 36
Generic 16 Logic Block
I/O Block ORP 16
Generic Logic Block
16 36
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LA-ispMACH 4000V/Z Automotive Family Data Sheet
The I/Os in the LA-ispMACH 4000V/Z automotive devices are split into two banks. Each bank has a separate I/O power supply. Inputs can support a variety of standards independent of the chip or bank power supply. Outputs support the standards compatible with the power supply provided to the bank. Support for a variety of standards helps designers implement designs in mixed voltage environments. In addition, 5V tolerant inputs are specified within an I/O bank that is connected to VCCO of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces.
LA-ispMACH 4000V/Z Automotive Architecture
There are a total of two GLBs in the LA-ispMACH 4032V/Z, increasing to 8 GLBs in the LA-ispMACH 4128V/Z. Each GLB has 36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into the GRP to be connected to the inputs of any other GLB on the device. Even if feedback signals return to the same GLB, they still must go through the GRP. This mechanism ensures that GLBs communicate with each other with consistent and predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them to the associated I/O cells in the I/O block.
Generic Logic Block
The LA-ispMACH 4000V/Z Automotive GLB consists of a programmable AND array, logic allocator, 16 macrocells and a GLB clock generator. Macrocells are decoupled from the product terms through the logic allocator and the I/O pins are decoupled from macrocells through the ORP. Figure 2 illustrates the GLB. Figure 2. Generic Logic Block
CLK0 CLK1 CLK2 CLK3 To GRP
Clock Generator
1+OE 16 MC Feedback Signals 1+OE
1+OE 1+OE 1+OE 1+OE 1+OE 1+OE To ORP To Product Term Output Enable Sharing
Logic Allocator
36 Inputs from GRP
AND Array
The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be connected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being fed to the macrocells. Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0. There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND Array.
AND Array 36 Inputs, 83 Product Terms
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16 Macrocells
Lattice Semiconductor
Figure 3. AND Array
In[0] In[34] In[35]
LA-ispMACH 4000V/Z Automotive Family Data Sheet
PT0 PT1 PT2 PT3 PT4
Cluster 0
PT75 PT76 PT77 Cluster 15 PT78 PT79 PT80 Shared PT Clock PT81 Shared PT Initialization PT82 Shared PTOE Note: Indicates programmable fuse.
Enhanced Logic Allocator
Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term cluster is associated with a macrocell. The cluster size for the LA-ispMACH 4000V/Z automotive family is 4+1 (total 5) product terms. The software automatically considers the availability and distribution of product term clusters as it fits the functions within a GLB. The logic allocator is designed to provide three speed paths: 5-PT fast bypass path, 20-PT Speed Locking path and an up to 80-PT path. The availability of these three paths lets designers trade timing variability for increased performance. The enhanced Logic Allocator of the LA-ispMACH 4000V/Z automotive family consists of the following blocks: * Product Term Allocator * Cluster Allocator * Wide Steering Logic Figure 4 shows a macrocell slice of the Logic Allocator. There are 16 such slices in the GLB. Figure 4. Macrocell Slice
to to n-1 n-2 from from n-1 n-4 Fast 5-PT Path 1-80 PTs To XOR (MC)
From n-4 n 5-PT
Cluster
to n+1 Individual Product Term Allocator
from n+2 Cluster Allocator
from n+1
To n+4 SuperWIDETM Steering Logic
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Lattice Semiconductor Product Term Allocator
LA-ispMACH 4000V/Z Automotive Family Data Sheet
The product term allocator assigns product terms from a cluster to either logic or control applications as required by the design being implemented. Product terms that are used as logic are steered into a 5-input OR gate associated with the cluster. Product terms that used for control are steered either to the macrocell or I/O cell associated with the cluster. Table 3 shows the available functions for each of the five product terms in the cluster. The OR gate output connects to the associated I/O cell, providing a fast path for narrow combinatorial functions, and to the logic allocator. Table 3. Individual PT Steering
Product Term PTn PTn+1 PTn+2 PTn+3 PTn+4 Logic Logic PT Logic PT Logic PT Logic PT Logic PT Single PT for XOR/OR Individual Clock (PT Clock) Individual Initialization or Individual Clock Enable (PT Initialization/CE) Individual Initialization (PT Initialization) Individual OE (PTOE) Control
Cluster Allocator
The cluster allocator allows clusters to be steered to neighboring macrocells, thus allowing the creation of functions with more product terms. Table 4 shows which clusters can be steered to which macrocells. Used in this manner, the cluster allocator can be used to form functions of up to 20 product terms. Additionally, the cluster allocator accepts inputs from the wide steering logic. Using these inputs, functions up to 80 product terms can be created. Table 4. Available Clusters for Each Macrocell
Macrocell M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 -- C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 Available Clusters C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 -- C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 -- --
Wide Steering Logic
The wide steering logic allows the output of the cluster allocator n to be connected to the input of the cluster allocator n+4. Thus, cluster chains can be formed with up to 80 product terms, supporting wide product term functions and allowing performance to be increased through a single GLB implementation. Table 5 shows the product term chains.
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Table 5. Product Term Expansion Capability
Expansion Chains Chain-0 Chain-1 Chain-2 Chain-3
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Macrocells Associated with Expansion Chain (with Wrap Around) M0 M4 M8 M12 M0 M1 M5 M9 M13 M1 M2 M6 M10 M14 M2 M3 M7 M11 M15 M3
Max PT/Macrocell 75 80 75 70
Every time the super cluster allocator is used, there is an incremental delay of tEXP . When the super cluster allocator is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super cluster is steered to M (n+4), then M (n) is ground).
Macrocell
The 16 macrocells in the GLB are driven by the 16 outputs from the logic allocator. Each macrocell contains a programmable XOR gate, a programmable register/latch, along with routing for the logic and control functions. Figure 5 shows a graphical representation of the macrocell. The macrocells feed the ORP and GRP. A direct input from the I/O cell allows designers to use the macrocell to construct high-speed input registers. A programmable delay in this path allows designers to choose between the fastest possible set-up time and zero hold time. Figure 5. Macrocell
Power-up Initialization
Shared PT Initialization PT Initialization (optional) PT Initialization/CE (optional) Delay From I/O Cell
From Logic Allocator
R D/T/L
P Q
To ORP To GRP
CE
Single PT
Block CLK0 Block CLK1 Block CLK2 Block CLK3 PT Clock (optional) Shared PT Clock
Enhanced Clock Multiplexer
The clock input to the flip-flop can select any of the four block clocks along with the shared PT clock, and true and complement forms of the optional individual term clock. An 8:1 multiplexer structure is used to select the clock. The eight sources for the clock multiplexer are as follows: * Block CLK0 * Block CLK1 * Block CLK2
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* * * * * Block CLK3 PT Clock PT Clock Inverted Shared PT Clock Ground
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Clock Enable Multiplexer
Each macrocell has a 4:1 clock enable multiplexer. This allows the clock enable signal to be selected from the following four sources: * PT Initialization/CE * PT Initialization/CE Inverted * Shared PT Clock * Logic High
Initialization Control
The LA-ispMACH 4000V/Z automotive family architecture accommodates both block-level and macrocell-level set and reset capability. There is one block-level initialization term that is distributed to all macrocell registers in a GLB. At the macrocell level, two product terms can be "stolen" from the cluster associated with a macrocell to be used for set/reset functionality. A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing flexibility. Note that the reset/preset swapping selection feature affects power-up reset as well. All flip-flops power up to a known state for predictable system initialization. If a macrocell is configured to SET on a signal from the block-level initialization, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a signal from the block-level initialization or is not configured for set/reset, then that macrocell will RESET on powerup. To guarantee initialization values, the VCC rise must be monotonic, and the clock must be inactive until the reset delay time has elapsed.
GLB Clock Generator
Each LA-ispMACH 4000V/Z automotive device has up to four clock pins that are also routed to the GRP to be used as inputs. These pins drive a clock generator in each GLB, as shown in Figure 6. The clock generator provides four clock signals that can be used anywhere in the GLB. These four GLB clock signals can consist of a number of combinations of the true and complement edges of the global clock signals. Figure 6. GLB Clock Generator
CLK0 Block CLK0
CLK1
Block CLK1
CLK2 Block CLK2
CLK3
Block CLK3
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Lattice Semiconductor Output Routing Pool (ORP)
LA-ispMACH 4000V/Z Automotive Family Data Sheet
The Output Routing Pool allows macrocell outputs to be connected to any of several I/O cells within an I/O block. This provides greater flexibility in determining the pinout and allows design changes to occur without affecting the pinout. The output routing pool also provides a parallel capability for routing macrocell-level OE product terms. This allows the OE product term to follow the macrocell output as it is switched between I/O cells. Additionally, the output routing pool allows the macrocell output or true and complement forms of the 5-PT bypass signal to bypass the output routing multiplexers and feed the I/O cell directly. The enhanced ORP of the LA-ispMACH 4000V/Z family consists of the following elements: * Output Routing Multiplexers * OE Routing Multiplexers * Output Routing Pool Bypass Multiplexers Figure 7 shows the structure of the ORP from the I/O cell perspective. This is referred to as an ORP slice. Each ORP has as many ORP slices as there are I/O cells in the corresponding I/O block. Figure 7. ORP Slice
OE Routing Multiplexer From PTOE To I/O Cell OE
5-PT Fast Path From Macrocell
ORP Bypass Multiplexer To I/O Cell Output
Output Routing Multiplexer
Output Routing Multiplexers
The details of connections between the macrocells and the I/O cells vary across devices and within a device dependent on the maximum number of I/Os available. Tables 6-10 provide the connection details. Table 6. ORP Combinations for I/O Blocks with 8 I/Os
I/O Cell I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 M0, M1, M2, M3, M4, M5, M6, M7 M2, M3, M4, M5, M6, M7, M8, M9 M4, M5, M6, M7, M8, M9, M10, M11 M6, M7, M8, M9, M10, M11, M12, M13 M8, M9, M10, M11, M12, M13, M14, M15 M10, M11, M12, M13, M14, M15, M0, M1 M12, M13, M14, M15, M0, M1, M2, M3 M14, M15, M0, M1, M2, M3, M4, M5 Available Macrocells
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Table 7. ORP Combinations for I/O Blocks with 16 I/Os
I/O Cell I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 M0, M1, M2, M3, M4, M5, M6, M7 M1, M2, M3, M4, M5, M6, M7, M8 M2, M3, M4, M5, M6, M7, M8, M9 M3, M4, M5, M6, M7, M8, M9, M10 M4, M5, M6, M7, M8, M9, M10, M11 M5, M6, M7, M8, M9, M10, M11, M12 M6, M7, M8, M9, M10, M11, M12, M13 M7, M8, M9, M10, M11, M12, M13, M14 M8, M9, M10, M11, M12, M13, M14, M15 M9, M10, M11, M12, M13, M14, M15, M0 M10, M11, M12, M13, M14, M15, M0, M1 M11, M12, M13, M14, M15, M0, M1, M2 M12, M13, M14, M15, M0, M1, M2, M3 M13, M14, M15, M0, M1, M2, M3, M4 M14, M15, M0, M1, M2, M3, M4, M5 M15, M0, M1, M2, M3, M4, M5, M6 Available Macrocells
Table 8. ORP Combinations for I/O Blocks with 12 I/Os
I/O Cell I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 M0, M1, M2, M3, M4, M5, M6, M7 M1, M2, M3, M4, M5, M6, M7, M8 M2, M3, M4, M5, M6, M7, M8, M9 M4, M5, M6, M7, M8, M9, M10, M11 M5, M6, M7, M8, M9, M10, M11, M12 M6, M7, M8, M9, M10, M11, M12, M13 M8, M9, M10, M11, M12, M13, M14, M15 M9, M10, M11, M12, M13, M14, M15, M0 M10, M11, M12, M13, M14, M15, M0, M1 M12, M13, M14, M15, M0, M1, M2, M3 M13, M14, M15, M0, M1, M2, M3, M4 M14, M15, M0, M1, M2, M3, M4, M5 Available Macrocells
ORP Bypass and Fast Output Multiplexers
The ORP bypass and fast-path output multiplexer is a 4:1 multiplexer and allows the 5-PT fast path to bypass the ORP and be connected directly to the pin with either the regular output or the inverted output. This multiplexer also allows the register output to bypass the ORP to achieve faster tCO.
Output Enable Routing Multiplexers
The OE Routing Pool provides the corresponding local output enable (OE) product term to the I/O cell.
I/O Cell
The I/O cell contains the following programmable elements: output buffer, input buffer, OE multiplexer and bus maintenance circuitry. Figure 8 details the I/O cell.
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Figure 8. I/O Cell
GOE 0 GOE 1 GOE 2 GOE 3 From ORP VCC
LA-ispMACH 4000V/Z Automotive Family Data Sheet
VCCO
VCCO From ORP To Macrocell To GRP
*Global fuses
*
* *
Each output supports a variety of output standards dependent on the VCCO supplied to its I/O bank. Outputs can also be configured for open drain operation. Each input can be programmed to support a variety of standards, independent of the VCCO supplied to its I/O bank. The I/O standards supported are: * LVTTL * LVCMOS 1.8 * LVCMOS 3.3 * 3.3V PCI Compatible * LVCMOS 2.5 All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, Pull-up Resistor or Pull-down Resistor. A fourth option is to provide none of these. The selection is done on a global basis. The default in both hardware and software is such that when the device is erased or if the user does not specify, the input structure is configured to be a Pull-up Resistor. Each LA-ispMACH 4000V/Z automotive device I/O has an individually programmable output slew rate control bit. Each output can be individually configured for fast slew or slow slew. The typical edge rate difference between fast and slow slew setting is 20%. For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reflections, less noise and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed.
Global OE Generation
Most LA-ispMACH 4000V/Z automotive family devices have a 4-bit wide Global OE Bus, except the LA-ispMACH 4032V and LA-ispMACH4032Z devices that have a 2-bit wide Global OE Bus. This bus is derived from a 4-bit internal global OE PT bus and two dual purpose I/O or GOE pins. Each signal that drives the bus can optionally be inverted. Each GLB has a block-level OE PT that connects to all bits of the Global OE PT bus with four fuses. Hence, for a 128-macrocell device (with 16 blocks), each line of the bus is driven from 8 OE product terms. Figures 9 and 10 show a graphical representation of the global OE generation.
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LA-ispMACH 4000V/Z Automotive Family Data Sheet
Figure 9. Global OE Generation for All Devices Except LA-ispMACH 4032V/Z
Internal Global OE PT Bus (4 lines) Global OE 4-Bit Global OE Bus
Shared PTOE (Block 0) Shared PTOE (Block n)
Global Fuses
Fuse connection Hard wired
GOE (0:3) to I/O cells
Figure 10. Global OE Generation for LA-ispMACH 4032V/Z
Internal Global OE PT Bus (2 lines)
Global OE
4-Bit Global OE Bus
Shared PTOE (Block 0) Shared PTOE (Block 1)
Global Fuses
Fuse connection Hard wired
GOE (3:0) to I/O cells
Zero Power/Low Power and Power Management
The LA-ispMACH 4000V/Z automotive family is designed with high speed low power design techniques to offer both high speed and low power. With an advanced E2 low power cell and non sense-amplifier design approach (full CMOS logic approach), the LA-ispMACH 4000V/Z automotive family offers SuperFAST pin-to-pin speeds, while simultaneously delivering low standby power without needing any "turbo bits" or other power management schemes associated with a traditional sense-amplifier approach.
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
The zero power LA-ispMACH 4000Z is based on the 1.8V ispMACH 4000C family. With innovative circuit design changes, the LA-ispMACH 4000Z family is able to achieve the industry's "lowest static power".
IEEE 1149.1-Compliant Boundary Scan Testability
All LA-ispMACH 4000V/Z automotive devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked into a board-level serial scan path for more board-level testing. The test access port operates with an LVCMOS interface that corresponds to the power supply voltage.
I/O Quick Configuration
To facilitate the most efficient board test, the physical nature of the I/O cells must be set before running any continuity tests. As these tests are fast, by nature, the overhead and time that is required for configuration of the I/Os' physical nature should be minimal so that board test time is minimized. The LA-ispMACH 4000V/Z automotive family of devices allows this by offering the user the ability to quickly configure the physical nature of the I/O cells. This quick configuration takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lattice's ispVMTM System programming software can either perform the quick configuration through the PC parallel port, or can generate the ATE or test vectors necessary for a third-party test system.
IEEE 1532-Compliant In-System Programming
Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inventory levels, higher quality and the ability to make in-field modifications. The LA-ispMACH 4000V/Z automotive devices provide In-System Programming (ISPTM) capability through the Boundary Scan Test Access Port. This capability has been implemented in a manner that ensures that the port remains complaint to the IEEE 1149.1 standard. By using IEEE 1149.1 as the communication interface through which ISP is achieved, users get the benefit of a standard, well-defined interface. All LA-ispMACH 4000V/Z automotive devices are also compliant with the IEEE 1532 standard. The LA-ispMACH 4000V/Z automotive devices can be programmed across the commercial temperature and voltage range. The PC-based Lattice software facilitates in-system programming of LA-ispMACH 4000V/Z automotive devices. The software takes the JEDEC file output produced by the design implementation software, along with information about the scan chain, and creates a set of vectors used to drive the scan chain. The software can use these vectors to drive a scan chain via the parallel port of a PC. Alternatively, the software can output files in formats understood by common automated test equipment. This equipment can then be used to program LAispMACH 4000V/Z automotive devices during the testing of a circuit board.
User Electronic Signature
The User Electronic Signature (UES) allows the designer to include identification bits or serial numbers inside the device, stored in E2CMOS memory. The LA-ispMACH 4000V/Z automotive device contains 32 UES bits that can be configured by the user to store unique data such as ID codes, revision numbers or inventory control codes.
Security Bit
A programmable security bit is provided on the LA-ispMACH 4000V/Z automotive devices as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. Programming and verification are also defeated by the security bit. The bit can only be reset by erasing the entire device.
Hot Socketing
The LA-ispMACH 4000V/Z automotive devices are well-suited for applications that require hot socketing capability. Hot socketing a device requires that the device, during power-up and down, can tolerate active signals on the I/Os
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LA-ispMACH 4000V/Z Automotive Family Data Sheet
and inputs without being damaged. Additionally, it requires that the effects of I/O pin loading be minimal on active signals. The LA-ispMACH 4000V/Z automotive devices provide this capability for input voltages in the range 0V to 3.0V.
Density Migration
The LA-ispMACH 4000V/Z automotive family has been designed to ensure that different density devices in the same package have the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design targeted for a high density device to a lower density device. However, the exact details of the final resource utilization will impact the likely success in each case.
AEC-Q100 Tested and Qualified
The Automotive Electronics Council (AEC) consists of two committees: the Quality Systems Committee and the Component Technical Committee. These committees are composed of representatives from sustaining and other associate members. The AEC Component Technical Committee is the standardization body for establishing standards for reliable, high quality electronic components. In particular, the AEC-Q100 specification "Stress Test for Qualification for Integrated Circuits" defines qualification and re-qualification requirements for electronic components. Components meeting these specifications are suitable for use in the harsh automotive environment without additional component-level qualification testing. Lattice's LA-ispMACH 4000V/Z and LA-MachXO devices completed and passed the requirements of the AEC-Q100 specification.
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LA-ispMACH 4000V/Z Automotive Family Data Sheet
Absolute Maximum Ratings1, 2, 3
LA-ispMACH 4000V (3.3V) LA-ispMACH 4000Z (1.8V) Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V . . . . . . . . . . . . . . . . -0.5 to 2.5V Output Supply Voltage (VCCO) . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . . . . . . . . -0.5 to 4.5V Input or I/O Tristate Voltage Applied4, 5 . . . . . . . . . . . . . . . . . -0.5 to 5.5V . . . . . . . . . . . . . . . . -0.5 to 5.5V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150C . . . . . . . . . . . . . . . -65 to 150C Junction Temperature (Tj) with Power Applied . . . . . . . . . . -55 to 150C . . . . . . . . . . . . . . . -55 to 150C
1. Stress above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. Undershoot of -2V and overshoot of (VIH (MAX) + 2V), up to a total pin voltage of 6.0V, is permitted for a duration of < 20ns. 5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed.
Recommended Operating Conditions
Symbol LA-ispMACH 4000V Supply Voltage VCC TA LA-ispMACH 4000Z Supply Voltage LA-ispMACH 4000Z, Extended Functional Voltage Operations Ambient Temperature (Automotive)
1. Devices operating at 1.6V can expect performance degradation up to 35%.
Parameter
Min. 3.0 1.7 1.6
1
Max. 3.6 1.9 1.9 125
Units V V V C
-40
Erase Reprogram Specifications
Parameter Erase/Reprogram Cycle
Note: Valid over commercial temperature range.
Min. 1,000
Max. --
Units Cycles
Hot Socketing Characteristics1,2,3
Symbol IDK
1. 2. 3.
Parameter Input or I/O Leakage Current
Condition 0 VIN 3.0V, Tj = 105C 0 VIN 3.0V, Tj = 130C
Min. -- --
Typ. 30 30
Max. 150 200
Units A A
Insensitive to sequence of VCC or VCCO. However, assumes monotonic rise/fall rates for VCC and VCCO, provided (VIN - VCCO) 3.6V. 0 < VCC < VCC (MAX), 0 < VCCO < VCCO (MAX). IDK is additive to IPU, IPD or IBH. Device defaults to pull-up until fuse circuitry is active.
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
I/O Recommended Operating Conditions
VCCO (V)1 Standard LVTTL LVCMOS 3.3 Extended LVCMOS 3.32 LVCMOS 2.5 LVCMOS 1.8 PCI 3.3 Min. 3.0 3.0 2.7 2.3 1.65 3.0 Max. 3.6 3.6 3.6 2.7 1.95 3.6
1. Typical values for VCCO are the average of the min. and max. values. 2. LA-ispMACH 4000Z only.
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol IIL, IIH1, 4 Parameter Input Leakage Current (LA-ispMACH 4000Z) Input High Leakage Current (LA-ispMACH 4000V) Input High Leakage Current (LA-ispMACH 4000Z) I/O Weak Pull-up Resistor Current (LA-ispMACH 4000V) I/O Weak Pull-up Resistor Current (LA-ispMACH 4000Z) Bus Hold Low Sustaining Current Bus Hold High Sustaining Current Bus Hold Low Overdrive Current Bus Hold High Overdrive Current Bus Hold Trip Points I/O Capacitance3 Clock Capacitance3 Global Input Capacitance3 Condition 0 VIN < VCCO 3.6V < VIN 5.5V, Tj = 105C 3.0V VCCO 3.6V 3.6V < VIN 5.5V, Tj = 130C 3.0V VCCO 3.6V VCCO < VIN 5.5V 0 VIN 0.7VCCO 0 VIN 0.7VCCO Min. -- -- -- -- -30 -30 30 30 -30 -- -- VCCO * 0.35 -- -- -- -- -- -- Typ. 0.5 -- -- -- -- -- -- -- -- -- -- -- 8 6 6 Max. 1 20 50 10 -200 -150 150 -- -- 150 -150 VCCO * 0.65 -- -- -- -- -- -- Units A A A A A A A A A A A V pf pf pf
IIH1, 2
IPU IPD IBHLS IBHHS IBHLO IBHHO VBHT C1 C2 C3
I/O Weak Pull-down Resistor Current VIL (MAX) VIN VIH (MIN) VIN = VIL (MAX) VIN = 0.7 VCCO 0V VIN VBHT VBHT VIN VCCO -- VCCO = 3.3V, 2.5V, 1.8V VCC = 1.8V, VIO = 0 to VIH (MAX) VCCO = 3.3V, 2.5V, 1.8V VCC = 1.8V, VIO = 0 to VIH (MAX) VCCO = 3.3V, 2.5V, 1.8V VCC = 1.8V, VIO = 0 to VIH (MAX)
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 2. 5V tolerant inputs and I/O should only be placed in banks where 3.0V VCCO 3.6V. 3. TA = 25C, f = 1.0MHz. 4. IIH excursions of up to 1.5A maximum per pin above the spec limit may be observed for certain voltage conditions on no more than 10% of the device's I/O pins.
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Supply Current, LA-ispMACH 4000V
Over Recommended Operating Conditions
Symbol LA-ispMACH 4032V ICC Operating Power Supply Current Standby Power Supply Current Operating Power Supply Current Standby Power Supply Current Operating Power Supply Current Standby Power Supply Current Vcc = 3.3V Vcc = 3.3V Vcc = 3.3V Vcc = 3.3V Vcc = 3.3V Vcc = 3.3V -- -- -- -- -- -- 11.8 11.3 12 11.5 12 11.5 -- -- -- -- -- -- mA mA mA mA mA mA Parameter Condition Min. Typ. Max. Units
LA-ispMACH 4064V ICC
LA-ispMACH 4128V ICC
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Supply Current, LA-ispMACH 4000Z
Over Recommended Operating Conditions
Symbol LA-ispMACH 4032Z Vcc = 1.8V, TA = 25C ICC1, 2, 3, 5 Operating Power Supply Current Vcc = 1.9V, TA = 70C Vcc = 1.9V, TA = 85C Vcc = 1.9V, TA = 125C Vcc = 1.8V, TA = 25C ICC4, 5 Standby Power Supply Current Vcc = 1.9V, TA = 70C Vcc = 1.9V, TA = 85C Vcc = 1.9V, TA = 125C LA-ispMACH 4064Z Vcc = 1.8V, TA = 25C ICC1, 2, 3, 5 Operating Power Supply Current Vcc = 1.9V, TA = 70C Vcc = 1.9V, TA = 85C Vcc = 1.9V, TA = 125C Vcc = 1.8V, TA = 25C ICC4, 5 Standby Power Supply Current Vcc = 1.9V, TA = 70C Vcc = 1.9V, TA = 85C Vcc = 1.9V, TA = 125C LA-ispMACH 4128Z Vcc = 1.8V, TA = 25C ICC1, 2, 3, 5 Operating Power Supply Current Vcc = 1.9V, TA = 70C Vcc = 1.9V, TA = 85C Vcc = 1.9V, TA = 125C Vcc = 1.8V, TA = 25C ICC4, 5 Standby Power Supply Current Vcc = 1.9V, TA = 70C Vcc = 1.9V, TA = 85C Vcc = 1.9V, TA = 125C
1. 2. 3. 4. 5.
Parameter
Condition
Min. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Typ. 50 58 60 70 10 13 15 22 80 89 92 109 11 15 18 37 168 190 195 212 12 16 19 42
Max. Units -- -- -- -- -- 20 25 A A A A A A A A -- -- -- -- -- 25 35 A A A A A A A A -- -- -- -- -- 35 50 -- A A A A A A A A
TA = 25C, frequency = 1.0 MHz. Device configured with 16-bit counters. ICC varies with specific device configuration and operating frequency. VCCO = 3.6V, VIN = 0V or VCCO, bus maintenance turned off. VIN above VCCO will add transient current above the specified standby ICC. Includes VCCO current without output loading.
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
I/O DC Electrical Characteristics
Over Recommended Operating Conditions
VIL Standard LVTTL LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 (4000V) LVCMOS 1.8 (4000Z) PCI 3.3 (4000V) PCI 3.3 (4000Z) Min (V) -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max (V) 0.80 0.80 0.70 0.63 0.35 * VCC 1.08 VIH Min (V) 2.0 2.0 1.70 1.17 0.65 * VCC 1.5 Max (V) 5.5 5.5 3.6 3.6 3.6 5.5 5.5 VOL Max (V) 0.40 0.20 0.40 0.20 0.40 0.20 0.40 0.20 0.40 0.20 0.1 VCCO 0.1 VCCO VOH Min (V) VCCO - 0.40 VCCO - 0.20 VCCO - 0.40 VCCO - 0.20 VCCO - 0.40 VCCO - 0.20 VCCO - 0.45 VCCO - 0.20 VCCO - 0.45 VCCO - 0.20 0.9 VCCO 0.9 VCCO IOL1 (mA) 8.0 0.1 8.0 0.1 8.0 0.1 2.0 0.1 2.0 0.1 1.5 1.5 IOH1 (mA) -4.0 -0.1 -4.0 -0.1 -4.0 -0.1 -2.0 -0.1 -2.0 -0.1 -0.5 -0.5
0.3 * 3.3 * (VCC / 1.8) 0.5 * 3.3 * (VCC / 1.8)
1. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND connections or between the last GND in a bank and the end of a bank.
100
3.3V VCCO
Typical I/O Output Current (mA)
IOL IOH
70 60 50 40 30 20 10 0 0 0.5
2.5V VCCO
Typical I/O Output Current (mA)
80 60 40 20 0
IOL IOH
0
0.5
1.0 1.5
2.0 2.5 3.0 3.5
1.0
1.5
2.0
2.5
VO Output Voltage (V)
VO Output Voltage (V)
60
1.8V VCCO
Typical I/O Output Current (mA)
50 40 30 20 10 0 0 0.5 1.0 1.5 2.0
IOL IOH
VO Output Voltage (V)
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4000V/Z External Switching Characteristics
Over Recommended Operating Conditions
LA-ispMACH 4000V -75 Parameter tPD tPD_MC tS tST tSIR tSIRZ tH tHT tHIR tHIRZ tCO tR tRW tPTOE/DIS tGPTOE/DIS tGOE/DIS tCW tGW tWIR fMAX
1. 2. 3. 4.
4
LA-ispMACH 4000Z -75 Min. -- -- 4.5 4.7 1.4 2.7 0.0 0.0 1.3 0.0 -- -- 4.0 -- -- -- 3.3 3.3 3.3 168 111 Max. 7.5 8.0 -- -- -- -- -- -- -- -- 4.5 9.0 -- 9.0 10.5 7.0 -- -- -- -- -- Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
Timing v.3.2
Description1, 2, 3 5-PT bypass combinatorial propagation delay 20-PT combinatorial propagation delay through macrocell GLB register setup time before clock GLB register setup time before clock with T-type register GLB register setup time before clock, input register path GLB register setup time before clock with zero hold GLB register hold time after clock GLB register hold time after clock with T-type register GLB register hold time after clock, input register path GLB register hold time after clock, input register path with zero hold GLB register clock-to-output delay External reset pin to output delay External reset pulse duration Input to output local product term output enable/disable Input to output global product term output enable/disable Global OE input to output enable/disable Global clock width, high or low Global gate width low (for low transparent) or high (for high transparent) Input register clock width, high or low Clock frequency with internal feedback
Min. -- -- 4.5 4.7 1.7 2.7 0.0 0.0 1.0 0.0 -- -- 4.0 -- -- -- 3.3 3.3 3.3 168 111
Max. 7.5 8.0 -- -- -- -- -- -- -- -- 4.5 9.0 -- 9.0 10.3 7.0 -- -- -- -- --
fMAX (Ext.) Clock frequency with external feedback, [1/ (tS + tCO)]
Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching. Pulse widths and clock widths less than minimum will cause unknown behavior. Standard 16-bit counter using GRP feedback.
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Timing Model
The task of determining the timing through the LA-ispMACH 4000V/Z automotive family, like any CPLD, is relatively simple. The timing model provided in Figure 11 shows the specific delay paths. Once the implementation of a given function is determined either conceptually or from the software report file, the delay path of the function can easily be determined from the timing model. The Lattice design tools report the timing delays based on the same timing model for a particular design. Note that the internal timing parameters are given for reference only, and are not tested. The external timing parameters are tested and guaranteed for every device. For more information on the timing model and usage, please refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines. Figure 11. LA-ispMACH 4000V/Z Automotive Timing Model
Routing/GLB Delays From Feedback tPDb tPDi IN tIN tIOI tROUTE tBLA tINREG tINDIO tMCELL tEXP
DATA
Q
tFBK tBUF tIOO tEN tDIS In/Out Delays
Feedback
tORP
Out
SCLK
tGCLK_IN tIOI
tPTCLK tBCLK tPTSR tBSR
C.E. S/R MC Reg.
Register/Latch Delays
Control Delays OE tGOE tIOI In/Out Delays
tGPTOE tPTOE
Note: Italicized items are optional delay adders.
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4000V/Z Internal Timing Parameters
Over Recommended Operating Conditions
LA-ispMACH 4000V -75 Parameter In/Out Delays tIN tGOE tGCLK_IN tBUF tEN tDIS tROUTE tMCELL tINREG tFBK tPDb tPDi tS tS_PT tST tST_PT tH tHT tSIR tSIR_PT tHIR tHIR_PT tCOi tCES tCEH tSL tSL_PT tHL tGOi tPDLi tSRi tSRR Control Delays tBCLK tPTCLK GLB PT Clock Delay Macrocell PT Clock Delay -- -- 1.12 0.87 -- -- 1.25 1.25 ns ns Input Buffer Delay Global OE Pin Delay Global Clock Input Buffer Delay Delay through Output Buffer Output Enable Time Output Disable Time Delay through GRP Macrocell Delay Input Buffer to Macrocell Register Delay Internal Feedback Delay 5-PT Bypass Propagation Delay Macrocell Propagation Delay D-Register Setup Time (Global Clock) D-Register Setup Time (Product Term Clock) T-Register Setup Time (Global Clock) T-Register Setup Time (Product Term Clock) D-Register Hold Time T-Register Hold Time D-Input Register Setup Time (Global Clock) D-Input Register Setup Time (Product Term Clock) D-Input Register Hold Time (Global Clock) D-Input Register Hold Time (Product Term Clock) Register Clock to Output/Feedback MUX Time Clock Enable Setup Time Clock Enable Hold Time Latch Setup Time (Global Clock) Latch Setup Time (Product Term Clock) Latch Hold Time Latch Gate to Output/Feedback MUX Time Propagation Delay through Transparent Latch to Output/Feedback MUX Asynchronous Reset or Set to Output/Feedback MUX Delay Asynchronous Reset or Set Recovery Time -- -- -- -- -- -- -- -- -- -- -- -- 1.57 1.32 1.77 1.32 2.93 2.93 1.57 1.45 1.18 1.18 -- 2.25 1.88 1.57 1.32 1.17 -- -- 0.28 1.67 1.50 6.04 2.28 1.50 0.96 0.96 2.26 1.45 0.96 0.00 2.24 1.24 -- -- -- -- -- -- -- -- -- -- 0.67 -- -- -- -- -- 0.33 0.25 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.35 2.45 1.55 2.75 3.15 3.15 0.75 1.45 1.95 1.18 -- 2.00 0.00 1.65 2.15 1.17 -- -- -- -- 1.80 4.30 2.15 1.30 2.70 2.70 2.50 1.00 1.00 0.05 1.90 1.00 -- -- -- -- -- -- -- -- -- -- 1.05 -- -- -- -- -- 0.33 0.25 0.28 1.67 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. LA-ispMACH 4000Z -75 Min. Max. Units
Routing/GLB Delays
Register/Latch Delays
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4000V/Z Internal Timing Parameters (Cont.)
Over Recommended Operating Conditions
LA-ispMACH 4000V -75 Parameter tBSR tPTSR tGPTOE tPTOE Description GLB PT Set/Reset Delay Macrocell PT Set/Reset Delay Global PT OE Delay Macrocell PT OE Delay Min. -- -- -- -- Max. 1.83 3.41 5.58 4.28 LA-ispMACH 4000Z -75 Min. -- -- -- -- Max. 1.83 2.72 3.50 2.00 Units ns ns ns ns
Timing v.3.2
Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details.
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4000V/Z Timing Adders1
LA-ispMACH 4000V -75 Adder Type tINDIO tEXP tORP tBLA LVTTL_in LVCMOS33_in LVCMOS25_in LVCMOS18_in PCI_in LVTTL_out Base Parameter tINREG tMCELL -- tROUTE Description Input register delay Product term expander delay Output routing pool delay Additional block loading adder Min. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 1.00 0.33 0.05 0.05 0.60 0.60 0.60 0.00 0.60 0.20 0.20 0.10 0.00 0.20 1.00 Optional Delay Adders -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.30 0.50 0.40 0.05 0.60 0.60 0.60 0.00 0.60 0.20 0.20 0.10 0.00 0.20 1.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LA-ispMACH 4000Z -75 Min. Max. Units
tIOI Input Adjusters tIN, tGCLK_IN, tGOE Using LVTTL standard tIN, tGCLK_IN, tGOE Using LVCMOS 3.3 standard tIN, tGCLK_IN, tGOE Using LVCMOS 2.5 standard tIN, tGCLK_IN, tGOE Using LVCMOS 1.8 standard tIN, tGCLK_IN, tGOE Using PCI compatible input tBUF, tEN, tDIS Output configured as TTL buffer Output configured as 3.3V buffer Output configured as 2.5V buffer Output configured as 1.8V buffer Output configured as PCI compatible buffer Output configured for slow slew rate
tIOO Output Adjusters LVCMOS33_out tBUF, tEN, tDIS LVCMOS25_out tBUF, tEN, tDIS LVCMOS18_out tBUF, tEN, tDIS PCI_out Slow Slew tBUF, tEN, tDIS tBUF, tEN
Note: Open drain timing is the same as corresponding LVCMOS timing. Timing v.3.2 1. Refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these adders.
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Boundary Scan Waveforms and Timing Specifications
Symbol tBTCP tBTCH tBTCL tBTSU tBTH tBRF tBTCO tBTOZ tBTVO tBTCPSU tBTCPH tBTUCO tBTUOZ tBTUOV TCK [BSCAN test] clock cycle TCK [BSCAN test] pulse width high TCK [BSCAN test] pulse width low TCK [BSCAN test] setup time TCK [BSCAN test] hold time TCK [BSCAN test] rise and fall time TAP controller falling edge of clock to valid output TAP controller falling edge of clock to data output disable TAP controller falling edge of clock to data output enable BSCAN test Capture register setup time BSCAN test Capture register hold time BSCAN test Update reg, falling edge of clock to valid output BSCAN test Update reg, falling edge of clock to output disable BSCAN test Update reg, falling edge of clock to output enable Parameter Min. 40 20 20 8 10 50 -- -- -- 8 10 -- -- -- Max. -- -- -- -- -- -- 10 10 10 -- -- 25 25 25 Units ns ns ns ns ns mV/ns ns ns ns ns ns ns ns ns
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Power Consumption
LA-ispMACH 4000V Typical ICC vs. Frequency
150 100
LA-ispMACH 4000Z Typical ICC vs. Frequency (Preliminary Information)
80
100
ICC (mA)
ICC (mA)
60
4128V
40 50
4064V 4032V
20
4128Z 4064Z 4032Z
0 0
50
100
150
200
250
300
350
400
0 0
50
100
150
200
250
300
Frequency (MHz)
Note: The devices are configured with the maximum number of 16-bit counters, typical current at 3.3V, 2.5V, 25C.
Frequency (MHz)
Note: The devices are configured with the maximum number of 16-bit counters, typical current at 1.8V, 25C.
Power Estimation Coefficients1
Device LA-ispMACH 4032V LA-ispMACH 4064V LA-ispMACH 4128V LA-ispMACH 4032Z LA-ispMACH 4064Z LA-ispMACH 4128Z A 11.3 11.5 11.5 0.010 0.011 0.012 B 0.010 0.010 0.011 0.010 0.010 0.010
1. For further information about the use of these coefficients, refer to Technical Note TN1005, Power Estimation in ispMACH 4000V/B/C/Z Devices.
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Switching Test Conditions
Figure 12 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 9. Figure 12. Output Test Load, LVTTL and LVCMOS Standards VCCO R1 DUT R2 CL Test Point
0213A/ispm4k
Table 9. Test Fixture Required Components
Test Condition LVCMOS I/O, (L -> H, H -> L) LVCMOS I/O (Z -> H) LVCMOS I/O (Z -> L) LVCMOS I/O (H -> Z) LVCMOS I/O (L -> Z)
1. CL includes test fixtures and probe capacitance.
R1
R2
CL1 35pF 35pF 35pF 5pF 5pF
Timing Ref. LVCMOS 3.3 = 1.5V LVCMOS 2.5 = VCCO/2 LVCMOS 1.8 = VCCO/2 1.5V 1.5V VOH - 0.3 VOL + 0.3
VCCO LVCMOS 3.3 = 3.0V LVCMOS 2.5 = 2.3V LVCMOS 1.8 = 1.65V 3.0V 3.0V 3.0V 3.0V
106 106 106 106 106 106
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Signal Descriptions
Signal Names TMS TCK TDI TDO GOE0/IO, GOE1/IO GND NC VCC CLK0/I, CLK1/I, CLK2/I, CLK3/I VCCO0, VCCO1 Description Input - This pin is the IEEE 1149.1 Test Mode Select input, which is used to control the state machine Input - This pin is the IEEE 1149.1 Test Clock input pin, used to clock through the state machine Input - This pin is the IEEE 1149.1 Test Data In pin, used to load data Output - This pin is the IEEE 1149.1 Test Data Out pin used to shift data out These pins are configured to be either Global Output Enable Input or as general I/O pins Ground Not Connected The power supply pins for the logic core and JTAG port These pins are configured to be either CLK input or as an input The power supply pins for each I/O bank Input/Output1 - These are the general purpose I/O used by the logic array. y is GLB reference (alpha) and z is macrocell reference (numeric). z: 0-15 yzz LA-ispMACH 4032V/Z LA-ispMACH 4064V/Z LA-ispMACH 4128V/Z
1. In some packages, certain I/Os are only available for use as inputs. See the signal connections table for details.
y: A-B y: A-D y: A-H
LA-ispMACH 4000V ORP Reference Table
4032V 4064V 4128V
Number of I/Os Number of GLBs Number of I/Os /GLB Reference ORP Table
301 2 16
32 2 16
302 4 8
32 4 8
64 4 16
64 8 8
923 8 12
96 8 12
16 I/Os / GLB
8 I/Os / GLB
16 I/Os / GLB 8 I/Os /GLB
12 I/Os / GLB
1. 32-macrocell device, 44 TQFP: 2 GLBs have 15 out of 16 I/Os bonded out. 2. 64-macrocells device, 44 TQFP: 2 GLBs have 7 out of 8 I/Os bonded out. 3. 128-macrocell device, 128 TQFP: 4 GLBs have 11 out of 12 I/Os
LA-ispMACH 4000Z ORP Reference Table
4032Z Number of I/Os Number of GLBs Number of I/Os / GLB Reference ORP Table 32 2 16 16 I/Os / GLB 32 4 8 8 I/Os / GLB 4064Z 64 4 16 16 I/Os / GLB 4128Z 64 8 8 8 I/Os / GLB
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4000V/Z Power Supply and NC Connections1
Signal VCC VCCO0 6 VCCO (Bank 0) VCCO1 28 VCCO (Bank 1) GND GND (Bank 0) GND (Bank 1) NC 12, 34 5 27 None 44 TQFP2 11, 33 48 TQFP2 12, 36 6 30 13, 37 5 29 None 100 TQFP2 25, 40, 75, 90 13, 33, 95 45, 63, 83 1, 26, 51, 76 7, 18, 32, 96 46, 57, 68, 82 None 128 TQFP2 32, 51, 96, 115 3, 17, 30, 41, 122 58, 67, 81, 94, 105 1, 33, 65, 97 10, 24, 40, 113, 123 49, 59, 74, 88, 104 None 144 TQFP2 36, 57, 108, 129 3, 19, 34, 47, 136 64, 75, 91, 106, 119 1, 37, 73, 109 10, 186, 27, 46, 127, 137 55, 65, 82, 906, 99, 118 17, 20, 38, 45, 72, 89, 92, 110, 117, 144
1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with the bank shown. 2. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise.
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4032V and 4064V Logic Signal Connections: 44-Pin TQFP
LA-ispMACH 4032V Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 GLB/MC/Pad TDI A5 A6 A7 GND (Bank 0) VCCO (Bank 0) A8 A9 A10 TCK VCC GND A12 A13 A14 A15 CLK2/I B0 B1 B2 B3 B4 TMS B5 B6 B7 GND (Bank 1) VCCO (Bank 1) B8 B9 B10 TDO VCC GND B12 B13 B14 B15/GOE1 CLK0/I A0/GOE0 A1 A2 ORP A^5 A^6 A^7 A^8 A^9 A^10 A^12 A^13 A^14 A^15 B^0 B^1 B^2 B^3 B^4 B^5 B^6 B^7 B^8 B^9 B^10 B^12 B^13 B^14 B^15 A^0 A^1 A^2 LA-ispMACH 4064V GLB/MC/Pad TDI A10 A12 A14 GND (Bank 0) VCCO (Bank 0) B0 B2 B4 TCK VCC GND B8 B10 B12 B14 CLK2/I C0 C2 C4 C6 C8 TMS C10 C12 C14 GND (Bank 1) VCCO (Bank 1) D0 D2 D4 TDO VCC GND D8 D10 D12 D14/GOE1 CLK0/I A0/GOE0 A2 A4 ORP A^5 A^6 A^7 B^0 B^1 B^2 B^4 B^5 B^6 B^7 C^0 C^1 C^2 C^3 C^4 C^5 C^6 C^7 D^0 D^1 D^2 D^4 D^5 D^6 D^7 A^0 A^1 A^2
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4032V and 4064V Logic Signal Connections: 44-Pin TQFP
LA-ispMACH 4032V Pin Number 43 44 Bank Number 0 0 GLB/MC/Pad A3 A4 ORP A^3 A^4 LA-ispMACH 4064V GLB/MC/Pad A6 A8 ORP A^3 A^4
LA-ispMACH 4032V/Z and 4064V/Z Logic Signal Connections: 48-Pin TQFP
LA-ispMACH 4032V/Z Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GLB/MC/Pad TDI A5 A6 A7 GND (Bank 0) VCCO (Bank 0) A8 A9 A10 A11 TCK VCC GND A12 A13 A14 A15 CLK1/I CLK2/I B0 B1 B2 B3 B4 TMS B5 B6 B7 GND (Bank 1) VCCO (Bank 1) B8 B9 B10 B11 TDO ORP A^5 A^6 A^7 A^8 A^9 A^10 A^11 A^12 A^13 A^14 A^15 B^0 B^1 B^2 B^3 B^4 B^5 B^6 B^7 B^8 B^9 B^10 B^11 LA-ispMACH 4064V/Z GLB/MC/Pad TDI A10 A12 A14 GND (Bank 0) VCCO (Bank 0) B0 B2 B4 B6 TCK VCC GND B8 B10 B12 B14 CLK1/I CLK2/I C0 C2 C4 C6 C8 TMS C10 C12 C14 GND (Bank 1) VCCO (Bank 1) D0 D2 D4 D6 TDO ORP A^5 A^6 A^7 B^0 B^1 B^2 B^3 B^4 B^5 B^6 B^7 C^0 C^1 C^2 C^3 C^4 C^5 C^6 C^7 D^0 D^1 D^2 D^3 -
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4032V/Z and 4064V/Z Logic Signal Connections: 48-Pin TQFP
LA-ispMACH 4032V/Z Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 Bank Number 1 1 1 1 1 0 0 0 0 0 0 GLB/MC/Pad VCC GND B12 B13 B14 B15/GOE1 CLK3/I CLK0/I A0/GOE0 A1 A2 A3 A4 ORP B^12 B^13 B^14 B^15 A^0 A^1 A^2 A^3 A^4 LA-ispMACH 4064V/Z GLB/MC/Pad VCC GND D8 D10 D12 D14/GOE1 CLK3/I CLK0/I A0/GOE0 A2 A4 A6 A8 ORP D^4 D^5 D^6 D^7 A^0 A^1 A^2 A^3 A^4
LA-ispMACH 4064V/Z and 4128V/Z Logic Signal Connections: 100-Pin TQFP
LA-ispMACH 4064V/Z Pin Number 1 2 3 4 5 6 7 8 9 10 11 12* 13 14 15 16 17 18 19 20 21 22 23* 24 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GLB/MC/Pad GND TDI A8 A9 A10 A11 GND (Bank 0) A12 A13 A14 A15 I VCCO (Bank 0) B15 B14 B13 B12 GND (Bank 0) B11 B10 B9 B8 I TCK ORP A^8 A^9 A^10 A^11 A^12 A^13 A^14 A^15 B^15 B^14 B^13 B^12 B^11 B^10 B^9 B^8 LA-ispMACH 4128V/Z GLB/MC/Pad GND TDI B0 B2 B4 B6 GND (Bank 0) B8 B10 B12 B13 I VCCO (Bank 0) C14 C12 C10 C8 GND (Bank 0) C6 C5 C4 C2 I TCK ORP B^0 B^1 B^2 B^3 B^4 B^5 B^6 B^7 C^7 C^6 C^5 C^4 C^3 C^2 C^1 C^0 -
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4064V/Z and 4128V/Z Logic Signal Connections: 100-Pin TQFP
LA-ispMACH 4064V/Z Pin Number 25 26 27* 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62* 63 64 65 66 67 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GLB/MC/Pad VCC GND I B7 B6 B5 B4 GND (Bank 0) VCCO (Bank 0) B3 B2 B1 B0 CLK1/I CLK2/I VCC C0 C1 C2 C3 VCCO (Bank 1) GND (Bank 1) C4 C5 C6 C7 GND TMS C8 C9 C10 C11 GND (Bank 1) C12 C13 C14 C15 I VCCO (Bank 1) D15 D14 D13 D12 ORP B^7 B^6 B^5 B^4 B^3 B^2 B^1 B^0 C^0 C^1 C^2 C^3 C^4 C^5 C^6 C^7 C^8 C^9 C^10 C^11 C^12 C^13 C^14 C^15 D^15 D^14 D^13 D^12 LA-ispMACH 4128V/Z GLB/MC/Pad VCC GND I D13 D12 D10 D8 GND (Bank 0) VCCO (Bank 0) D6 D4 D2 D0 CLK1/I CLK2/I VCC E0 E2 E4 E6 VCCO (Bank 1) GND (Bank 1) E8 E10 E12 E14 GND TMS F0 F2 F4 F6 GND (Bank 1) F8 F10 F12 F13 I VCCO (Bank 1) G14 G12 G10 G8 ORP D^7 D^6 D^5 D^4 D^3 D^2 D^1 D^0 E^0 E^1 E^2 E^3 E^4 E^5 E^6 E^7 F^0 F^1 F^2 F^3 F^4 F^5 F^6 F^7 G^7 G^6 G^5 G^4
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4064V/Z and 4128V/Z Logic Signal Connections: 100-Pin TQFP
LA-ispMACH 4064V/Z Pin Number 68 69 70 71 72 73* 74 75 76 77* 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
*This pin is input only.
LA-ispMACH 4128V/Z GLB/MC/Pad GND (Bank 1) G6 G5 G4 G2 I TDO VCC GND I H13 H12 H10 H8 GND (Bank 1) VCCO (Bank 1) H6 H4 H2 H0/GOE1 CLK3/I CLK0/I VCC A0/GOE0 A2 A4 A6 VCCO (Bank 0) GND (Bank 0) A8 A10 A12 A14 ORP G^3 G^2 G^1 G^0 H^7 H^6 H^5 H^4 H^3 H^2 H^1 H^0 A^0 A^1 A^2 A^3 A^4 A^5 A^6 A^7
Bank Number 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
GLB/MC/Pad GND (Bank 1) D11 D10 D9 D8 I TDO VCC GND I D7 D6 D5 D4 GND (Bank 1) VCCO (Bank 1) D3 D2 D1 D0/GOE1 CLK3/I CLK0/I VCC A0/GOE0 A1 A2 A3 VCCO (Bank 0) GND (Bank 0) A4 A5 A6 A7
ORP D^11 D^10 D^9 D^8 D^7 D^6 D^5 D^4 D^3 D^2 D^1 D^0 A^0 A^1 A^2 A^3 A^4 A^5 A^6 A^7
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4128V Logic Signal Connections: 128-Pin TQFP
LA-ispMACH 4128V Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GLB/MC/Pad GND TDI VCCO (Bank 0) B0 B1 B2 B4 B5 B6 GND (Bank 0) B8 B9 B10 B12 B13 B14 VCCO (Bank 0) C14 C13 C12 C10 C9 C8 GND (Bank 0) C6 C5 C4 C2 C0 VCCO (Bank 0) TCK VCC GND D14 D13 D12 D10 D9 D8 GND (Bank 0) VCCO (Bank 0) D6 ORP B^0 B^1 B^2 B^3 B^4 B^5 B^6 B^7 B^8 B^9 B^10 B^11 C^11 C^10 C^9 C^8 C^7 C^6 C^5 C^4 C^3 C^2 C^0 D^11 D^10 D^9 D^8 D^7 D^6 D^5
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4128V Logic Signal Connections: 128-Pin TQFP (Cont.)
LA-ispMACH 4128V Pin Number 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Bank Number 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GLB/MC/Pad D5 D4 D2 D1 D0 CLK1/I GND (Bank 1) CLK2/I VCC E0 E1 E2 E4 E5 E6 VCCO (Bank 1) GND (Bank 1) E8 E9 E10 E12 E14 GND TMS VCCO (Bank 1) F0 F1 F2 F4 F5 F6 GND (Bank 1) F8 F9 F10 F12 F13 F14 VCCO (Bank 1) G14 G13 G12 G10 ORP D^4 D^3 D^2 D^1 D^0 E^0 E^1 E^2 E^3 E^4 E^5 E^6 E^7 E^8 E^9 E^11 F^0 F^1 F^2 F^3 F^4 F^5 F^6 F^7 F^8 F^9 F^10 F^11 G^11 G^10 G^9 G^8
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4128V Logic Signal Connections: 128-Pin TQFP (Cont.)
LA-ispMACH 4128V Pin Number 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Bank Number 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GLB/MC/Pad G9 G8 GND (Bank 1) G6 G5 G4 G2 G0 VCCO (Bank 1) TDO VCC GND H14 H13 H12 H10 H9 H8 GND (Bank 1) VCCO (Bank 1) H6 H5 H4 H2 H1 H0/GOE1 CLK3/I GND (Bank 0) CLK0/I VCC A0/GOE0 A1 A2 A4 A5 A6 VCCO (Bank 0) GND (Bank 0) A8 A9 A10 A12 A14 ORP G^7 G^6 G^5 G^4 G^3 G^2 G^0 H^11 H^10 H^9 H^8 H^7 H^6 H^5 H^4 H^3 H^2 H^1 H^0 A^0 A^1 A^2 A^3 A^4 A^5 A^6 A^7 A^8 A^9 A^11
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4128V Logic Signal Connections: 144-Pin TQFP
LA-ispMACH 4128V Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GLB/MC/Pad GND TDI VCCO (Bank 0) B0 B1 B2 B4 B5 B6 GND (Bank 0) B8 B9 B10 B12 B13 B14 NC GND (Bank 0) NC C14 C13 C12 C10 C9 C8 GND (Bank 0) C6 C5 C4 C2 C1 C0 VCCO (Bank 0) TCK VCC GND NC D14 D13 D12 D10
1
ORP B^0 B^1 B^2 B^3 B^4 B^5 B^6 B^7 B^8 B^9 B^10 B^11 C^11 C^10 C^9 C^8 C^7 C^6 C^5 C^4 C^3 C^2 C^1 C^0 D^11 D^10 D^9 D^8
VCCO (Bank 0)
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4128V Logic Signal Connections: 144-Pin TQFP (Cont.)
LA-ispMACH 4128V Pin Number 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GLB/MC/Pad D9 D8 NC GND (Bank 0) VCCO (Bank 0) D6 D5 D4 D2 D1 D0 CLK1/I GND (Bank 1) CLK2/I VCC E0 E1 E2 E4 E5 E6 VCCO (Bank 1) GND (Bank 1) E8 E9 E10 E12 E13 E14 NC GND TMS VCCO (Bank 1) F0 F1 F2 F4 F5 F6 GND (Bank 1) F8 F9 F10 ORP D^7 D^6 D^5 D^4 D^3 D^2 D^1 D^0 E^0 E^1 E^2 E^3 E^4 E^5 E^6 E^7 E^8 E^9 E^10 E^11 F^0 F^1 F^2 F^3 F^4 F^5 F^6 F^7 F^8
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4128V Logic Signal Connections: 144-Pin TQFP (Cont.)
LA-ispMACH 4128V Pin Number 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Bank Number 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 GLB/MC/Pad F12 F13 F14 NC GND (Bank 1) NC G14 G13 G12 G10 G9 G8 GND (Bank 1) G6 G5 G4 G2 G1 G0 VCCO (Bank 1) TDO VCC GND NC H14 H13 H12 H10 H9 H8 NC GND (Bank 1) VCCO (Bank 1) H6 H5 H4 H2 H1 H0/GOE1 CLK3/I GND (Bank 0) CLK0/I
1
ORP F^9 F^10 F^11 G^11 G^10 G^9 G^8 G^7 G^6 G^5 G^4 G^3 G^2 G^1 G^0 H^11 H^10 H^9 H^8 H^7 H^6 H^5 H^4 H^3 H^2 H^1 H^0 -
VCCO (Bank 1)
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4128V Logic Signal Connections: 144-Pin TQFP (Cont.)
LA-ispMACH 4128V Pin Number 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GLB/MC/Pad VCC A0/GOE0 A1 A2 A4 A5 A6 VCCO (Bank 0) GND (Bank 0) A8 A9 A10 A12 A13 A14 NC2 ORP A^0 A^1 A^2 A^3 A^4 A^5 A^6 A^7 A^8 A^9 A^10 A^11 -
1. For device migration considerations, these NC pins are GND pins for I/O banks in LA-ispMACH 4128V devices.
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Part Number Description
LA XXXX XX - XX XX XXX X
Device Family Device Number 4032 = 32 Macrocells 4064 = 64 Macrocells 4128 = 128 Macrocells Power Blank = Low Power Z = Zero Power Supply Voltage V = 3.3V C = 1.8V Speed 75 = 7.5ns Operating Temperature Range E = Automotive Pin/Ball Count 44 (1.0mm thickness) 48 (1.0mm thickness) 100 128 144 Package TN = Lead-free TQFP
Ordering Information
Device LA4032V Part Number LA4032V-75TN48E LA4032V-75TN44E LA4064V-75TN100E LA4064V LA4064V-75TN48E LA4064V-75TN44E LA4128V-75TN144E LA4128V LA4032Z LA4064Z LA4128Z LA4128V-75TN128E LA4128V-75TN100E LA4032ZC-75TN48E LA4064ZC-75TN100E LA4064ZC-75TN48E LA4128ZC-75TN100E Macrocells 32 32 64 64 64 128 128 128 32 64 64 128 Voltage 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 1.8 1.8 1.8 1.8 tPD 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 Package Lead-free TQFP Lead-free TQFP Lead-free TQFP Lead-free TQFP Lead-free TQFP Lead-free TQFP Lead-free TQFP Lead-free TQFP Lead-free TQFP Lead-free TQFP Lead-free TQFP Lead-free TQFP Pin/Ball Count 48 44 100 48 44 144 128 100 48 100 48 100 I/O 32 30 64 32 30 96 92 64 32 64 32 64 Grade E E E E E E E E E E E E
Automotive Disclaimer
Products are not designed, intended or warranted to be fail-safe and are not designed, intended or warranted for use in applications related to the deployment of airbags. Further, products are not intended to be used, designed or warranted for use in applications that affect the control of the vehicle unless there is a fail-safe or redundancy feature and also a warning signal to the operator of the vehicle upon failure. Use of products in such applications is fully at the risk of the customer, subject to applicable laws and regulations governing limitations on product liability.
For Further Information
In addition to this data sheet, the following technical notes may be helpful when designing with the LA-ispMACH 4000V/Z automotive family: * ispMACH 4000 Timing Model Design and Usage Guidelines (TN1004) * ispMACH 4000V/B/C/Z Power Consumption (TN1005)
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Revision History
Date April 2006 October 2006 March 2007 September 2007 July 2008 Version 01.0 02.0 02.1 02.2 02.3 Initial release. Added LA-ispMACH 4000Z support information throughout. Updated ispMACH 4000 Introduction section. Updated Signal Descriptions table. DC Electrical Characteristics table, removed duplicate specifications. Lowered the maximum supply current at 85C to match the commercial product values. Added automotive disclaimer. Change Summary
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